Name: Stallion S100
Brand: Fairview

Identities

B_stack = (W_DQ × R_pin) / 8000 TB/s

B_agg = B_stack × N_stacks

t_CK = 2 / R_pin ns (DDR; 8 Gbps ⇒ 0.250 ns)

C_GB = N_hi × D_die,Gb / 8

P_FP32 = N_SM × N_ALU × 2 × f_GHz / 1000000 PFLOPS

Worked first package

2048-bit × 8 Gbps / 8 = 2.048 TB/s per stack. Eight stacks = 16.0 TB/s sustained across an aggregate 16,384-bit wide bus. 16-Hi × 32 Gb / 8 = 64 GB per stack. Eight cubes = 512 GB unified HBM4 memory pool on 3Dx3D Glass Core Substrate.

SPHBM4 identity match

Same DRAM stacks, 512-bit external interface, 4:1 serialization. 512 × 32 / 8000 = 2.048 TB/s if and only if the external rate is the 4×8 identity. That is arithmetic, not a datasheet bin.

What we will not write

Invent unpublished JEDEC timings (tRFC, tREFI, tRCD, tRP, tRAS, tFAW, tCCD).
Select a FairView VDDQ or VDDC. The legal sets are vendor-specific options.
Lock Samsung 11.7 Gbps, SK hynix 10 GT/s, or SPHBM4 46 GT/s as FairView numbers.
Claim FairView owns the 1T1C DRAM array or a secret cell process.
Treat UCIe, CXL.mem, or optical I/O as on-package HBM bandwidth.
Write 128 GB/s PCIe as if it were Gallium TB/s.
Claim unfiled IP. Five pillars are internal invention-disclosure directions only.
Quote 2 TB/s from a 2048-bit teaching lock, or confuse 8×1024 with 8×2048 (16,384-bit HBM4).
Present FV-Link 4.0 optics as shipped or measured. Phase 1 is electrical; 1.8 TB/s, 0.05 dB/cm @ 1550nm, <20ns, 512 MPUs, 256 TB direct and 1.5 PB CXL are Phase 2 (2029+) design targets pending PIC MPW validation.

Interconnect roadmap · Two phases

Phase 1 electrical. Phase 2 optical.

The identity rules above describe the architecture under tape-out: electrical HBM4 over direct Cu-Cu hybrid bonding on a 3.2 ppm/K glass core substrate. FV-Link 4.0 — CPO-Ready Platform is the Phase 2 (2029+) optical unlock. Its numbers are design targets, and we label them as such rather than as measurements.

Phase 1 Electrical → Phase 2 OpticalPhase 1 ships electrical

Phase 1Now → H2-27Shipping — Electrical

Electrical HBM4 + Stallion S10 MPU

Phase 1 Now-H2-27 — Electrical HBM4 + Stallion S10 MPU — MPW H1-27, Production H2-27 — CPO-Ready glass interposer

Phase 1 is the actual product. Gallium HBM4 delivers 16.0 TB/s across the 16,384-bit aggregate bus to the Stallion S10 MPU over direct Cu-Cu hybrid bonding on a 3.2 ppm/K glass core substrate. The same substrate ships with a laser-inscribed waveguide trench reserved in the layout — so the Phase 2 optical unlock is a substrate and packaging evolution, not a re-architecture. No optical engine is present in Phase 1 silicon.

Gallium HBM4 co-designed memory subsystem — 16.0 TB/s target, 512 GB target capacity
Stallion S10 MPU — 2nm-class GAAFET compute, TSMC-SoIC direct Cu-Cu hybrid bonding
3Dx3D glass core substrate, 3.2 ppm/K, CTE matched — laser-inscribed trench reserved for future 1550nm routing
CPO-Ready glass interposer: waveguide trench and optical land reserved, not populated — bypasses copper SerDes heat by design
MPW tape-out H1-27 · Production silicon H2-27 · Engineering-Ordered units 2028

16.0 TB/s

HBM4 Aggregate Bandwidth

Target · Electrical HBM4

3.2 ppm/K

Glass Core CTE Match

Material property · Substrate spec

H1-27

MPW Tape-Out

Committed milestone

Phase 22029+Target — Not in Phase 1 silicon

Phase 2 (2029+) Optical Unlock — Target

FV-Link 4.0 — CPO-Ready Glass Platform — Phase 2 (2029+) Optical Unlock — Target

Phase 2 populates the reserved trench and attaches on-package optical engines. Fairview is not claiming a shipping photonic product today — these are simulation-derived design targets from partner PDK modelling, gated on a photonic integrated circuit (PIC) multi-project wafer shuttle at Tower Semiconductor, GlobalFoundries Fotonix, or imec. Until that MPW returns measured data, every optical number below is a target, not a result.

Target 1.8 TB/s On-Package Optical Engine (CPO-Ready) — bi-directional per MPU; PHY reserve present in Phase 1
Target 0.05 dB/cm @1550nm — Simulated, Waveguide Path Reserved, Pending PIC MPW Validation
Glass core substrate 3.2 ppm/K — CTE matched, laser-inscribed trench reserved for future 1550nm routing; design bypasses copper SerDes heat
Phase 2 (2029+) Optical Unlock — Target: <20ns inter-chassis optical clustering across up to 512 MPUs
Phase 2 (2029+) Optical Unlock — Target: 256 TB direct HBM4 / 1.5 PB disaggregated CXL memory domain
Validation gate: Tower / GlobalFoundries Fotonix / imec PIC MPW silicon bring-up

1.8 TB/s

Target 1.8 TB/s On-Package Optical Engine (CPO-Ready)

Design Target · Simulated · Pending PIC MPW

0.05 dB/cm

Target 0.05 dB/cm @1550nm — Simulated, Waveguide Path Reserved, Pending PIC MPW Validation

Design Target · Not Measured

512

MPUs in Coherent Domain

Phase 2 Target

Handoff railPhase 1 substrate, RDL, and package land patterns are drawn so the FV-Link 4.0 — CPO-Ready Platform optical engine can be attached without a package re-spin. Optical unlock is gated on PIC MPW bring-up, not on a package redesign.

All optical specs are design targets based on simulation / partner PDK — pending Tower / GlobalFoundries Fotonix / imec PIC MPW validation. Phase 1 ships electrical.

FairView policy

Five architectural mechanisms. Proprietary trade secrets.

These are proprietary product architectures and trade secret claim directions. JEDEC maps, DRFM, and UCIe itself are not ours.

Dual-mode, one QoS plane

JESD270-4 (2048-bit interposer) and JESD330-4 (512-bit organic, 4:1) present the same 32 logical channels and the same credit plane to Stallion. First tape-out is H4-only; the S4 wrapper is a stub.

MPU-scheduled refresh

Stallion issues idle-window credits from wavefront drain, barriers, and L2 miss-queue occupancy. Gallium prefers those windows for refresh and directed refresh. Periodic refresh still fires if credits do not arrive.

Channel virtualization

A firmware remap table isolates MIG tenants or a second Stallion die. The stack always sees legal CH0–CH31. Remap is drain-then-commit — never mid-burst.

UCIe sidecar, not the data path

Command, credit, thermal class, and RAS events ride a closed opcode set. There is no data-beat type. HBM read/write never rides UCIe.

Fused thermal class

Cube, controller, and SM sensors fuse into four discrete classes. Class raises refresh weight, demotes unhinted QoS, and at class 3 requests a Stallion clock re-lock. No invented junction-temperature datasheet.

Sidecar opcode classes. There is no data-beat type. Sidecar FIFO width × rate is not B_stack.
Opcode	Direction	Payload
CREDIT_UPD	Gallium → Stallion	Per-PC / per-class credits
HINT_WINDOW	Stallion → Gallium	Idle-cycle grant, urgency
THERM_BIN	Both	Discrete thermal class 0–3
RAS_EVENT	Gallium → Stallion	Poison, replay, channel down
MAP_COMMIT	Stallion → Gallium	Remap table CRC
LINK_HB	Both	Heartbeat

All optical specs are design targets based on simulation / partner PDK — pending Tower / GlobalFoundries Fotonix / imec PIC MPW validation. Phase 1 ships electrical.